Financial SoftwareSilexica Expands Into FinTech Industry Bringing Next-Generation Compute Acceleration

Empowering Financial Services with SLX FPGA for Improved Performance and Time-to-Market
PRNewswire PRNewswireJune 3, 20203 min

Silexica (SLX) silexica.com has announced its entry into the FinTech industry to help financial service companies and exchanges leverage next-generation compute acceleration for improved latency/throughput, determinism, risk management, security, performance per watt, and total cost of ownership (TCO). Silexica’s SLX Tool Suite empowers software and hardware engineers to deeply analyze and optimize C/C++ algorithms for high-level synthesis (HLS) implementation in FPGA designs to improve performance and time-to-market.

“Silexica’s engagements with several financial companies and exchanges showed that SLX FPGA makes it even easier to go from software to optimized hardware accelerators and provides solutions for critical industry challenges, such as improved latency and determinism,” said Maximilian Odendahl, CEO of Silexica. “We’re excited to be an active member of STAC and to contribute to the future of electronic trading by democratizing accelerated computing.” 

An active member of the Securities Technology Analysis Center (STAC), Silexica will be presenting at the Global STAC Summit™ to discuss important technical challenges in trading and investment.

Event: Global STAC Live, Spring 2020

Date & TimeJune 2-4, 20208:30 a.m.-12:30 p.m., NY (GMT-4)

Topic: FPGA Accelerators: How to beat RTL design latency in a fraction of the time

Enabling the next generation of compute acceleration for financial services

In an ever-connected world, the speed and security of financial markets drive the global economy. With the ability to support higher compute requirements, financial institutions can now leverage programmable hardware (FPGAs) and high-level synthesis (HLS) design methodologies. With SLX FPGA, software professionals can meet these challenging system requirements with automated software optimization based on disruptive compiler technology.

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